Datasheet4U Logo Datasheet4U.com

ICS874005-04 - PCI EXPRESS JITTER ATTENUATOR

General Description

The ICS874005-04 is a high performance DiffIC S erential-to-LVDS Jitter Attenuator designed for use HiPerClockS™ in PCI Express systems.

Key Features

  • Five differential LVDS output pairs.
  • One differential clock input.
  • Supports 100MHz, 125MHz, and 250MHz Serdes reference clocks.
  • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
  • Output frequency range: 98MHz - 320MHz.
  • Input frequency range: 98MHz - 128MHz.
  • PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant.
  • RMS phase jitter @ 100MHz (1.875MHz.
  • 20MHz): 0.88ps (typical).

📥 Download Datasheet

Datasheet Details

Part number ICS874005-04
Manufacturer Integrated Device Technology
File Size 303.33 KB
Description PCI EXPRESS JITTER ATTENUATOR
Datasheet download datasheet ICS874005-04 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com PCI EXPRESS™ JITTER ATTENUATOR ICS874005-04 GENERAL DESCRIPTION The ICS874005-04 is a high performance DiffIC S erential-to-LVDS Jitter Attenuator designed for use HiPerClockS™ in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874005-04 has 2 PLL bandwidth modes: 300kHz and 2MHz. The 300kHz mode will provide maximum jitter attenuation, but higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated.